Platform IO DMA Transaction Acceleration

Computer system IO (with accelerator, network, storage, graphics components) has been optimized to use descriptor-based direct memory access (DMA) operations to move data to and from relatively fast addressable system (or main) memory or cache structures. Traditionally, transactions between slower IO sub-systems and system memory have been done using a host bus/bridge adapter (HBA). Each IO interface has one or more separately instantiated descriptor-based DMA engines optimized for a given IO port. As heterogeneous cores multiply in exascale systems, IO traffic can be expected to be more complex and will require more resources. This paper measures the descriptor overhead and analyzes its impact on latency and bandwidth. Based on quantifications of the latency and bandwidth overhead, we propose to improve IO performance using an integrated platform IO accelerator. This IO engine localizes IO transactions to the processor CPU, rather than offloading to various remote platform interface controllers. By simplifying hardware control of IO in complex systems that rely on a central system memory, we conclude there are quantifiable benefits of integrated platform IO transactions in terms of bandwidth-per-pin and latency, and other areas.